The present invention relates generally to computer systems and, more particularly, to a processor having a tagging buffer, a computer system including the processor, and methods for avoiding memory collisions during execution of program instruction pairs.
In fashion pipelines, load instructions typically have priority over store instructions because load instructions should be executed faster than store instructions. As such, the execution of certain program instruction pairs, e.g., <st reg, [mem1]; Id [mem2], reg>, may degrade performance when the memory addresses are the same, i.e., mem1=mem2. The reason for this is that the CPU may execute the higher priority load operation first. This change in the order of execution will usually increase performance, however, when the memory addresses specified in the instruction pair are the same, a memory collision occurs and the wrong value will be loaded into the register, as explained in more detail below with reference to FIG. 1. To correct this error, the load instruction and all dependents of the load instruction should be discarded and then reissued and re-executed. Surely, this will degrade the execution performance significantly.
FIG. 1 is a schematic diagram that illustrates an exemplary error that may occur when an instruction pair that specifies the same memory address is executed in a different order. The exemplary instruction pair to be executed is <st reg1[mem1]; Id [mem2] reg2>and mem1=mem2, i.e., the memory addresses are the same. As shown in FIG. 1, registers 100 include registers 1 and 2 and memory 110 includes mem1 and mem2, which indicate the same memory address. The value in register 1 is X and the store instruction calls for this value to be stored in mem1. The load instruction then calls for the contents of mem2 to be loaded into register 2. Because X is to be loaded into mem1 and mem1=mem2, the desired contents of mem2 to be loaded into register 2 is the value X. However, when the load instruction is executed first, i.e., before the store instruction, the value Y, which is the original contents of mem2, will be incorrectly loaded into register 2, as shown in FIG. 1.
In view of the foregoing, there is a need for a method of identifying instruction pairs that refer to the same memory address at an early stage so that these instruction pairs can be executed in the proper order.